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325 mhz, 8 8 buffered video crosspoint switches ad8108/ad8109 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. eatures 8 8 high speed nonblocking switch arrays ad8108: g = 1 ad8109: g = 2 serial or parallel programming of switch array serial data out allows daisy-chaining of multiple 8 8 arrays to create larger switch arrays output disable allows connection of multiple devices pin-compatible with ad8110/ad8111 16 8 switch arrays for 16 16 arrays see ad8116 complete solution buffered inputs eight output amplifiers ad8108 (g = 1) ad8109 (g = 2) drives 150 loads excellent video performance 60 mhz 0.1 db gain flatness 0.02%/0.02 differential gain/differential phase error (r l = 150 ) excellent ac performance ?3 db bandwidth: 325 mhz (ad8108), 250 mhz (ad8109) slew rate: 400 v/s (ad8108), 480 v/s (ad8109) low power of 45 ma low all hostile crosstalk of ?83 db @ 5 mhz reset pin allows disabling of all outputs (connected through a capacitor to ground provides power-on reset capability) excellent esd rating: exceeds 4000 v human body model 80-lead lqfp (12 mm 12 mm) applications routing of high speed signals including composite video (ntsc, pal, s, secam) component video (yuv, rgb) compressed video (mpeg, wavelet) 3-level digital video (hdb3) general description the ad8108/ad8109 are high speed 8 8 video crosspoint switch matrices. they offer a ?3 db signal bandwidth greater than 250 mhz and channel switch times of less than 25 ns with 1% settling. with ?83 db of crosstalk and ?98 db isolation (@5 mhz), the ad8108/ad8109 are useful in many high speed applications. the differential gain and differential phase of better than 0.02% functional block diagram ad8108/ad8109 switch matrix output buffer g = +1 g = +2 32 32 64 32-bit shift register with 4-bit parallel loading parallel latch decode 8 ? 4:8 decoders 8 clk data in update ce reset 8 inputs a0 data out 8 outputs set individual or reset all outputs to "off" a1 a2 ser/par d0 d1 d2 d3 enable/disable 01068-001 figure 1. functional block diagram and 0.02, respectively, along with 0.1 db flatness out to 60 mhz, make the ad8108/ad8109 ideal for video signal switching. the ad8108 and ad8109 include eight independent output buffers that can be placed into a high impedance state for paral- leling crosspoint outputs so that off channels do not load the output bus. the ad8108 has a gain of 1, while the ad8109 offers a gain of 2. they operate on voltage supplies of 5 v while consuming only 45 ma of idle current. the channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control allowing updating of an individual output without re-programming the entire array. the ad8108/ad8109 is packaged in an 80-lead lqfp package and is available over the extended industrial temperature range of ?40c to +85c.
important links for the ad8108_8109 * last content update 08/23/2013 02:21 pm parametric selection tables find similar products by operating parameters high speed switches documentation an-282: fundamentals of sampled data systems data-acquisition system uses fault protection cmos switches offer high performance in low power, wideband applications enhanced multiplexing for mems optical cross connects for the ad8108 an-214: ground rules for high speed circuits evaluation kits & symbols & footprints view the evaluation boards and kits page for the ad8108 view the evaluation boards and kits page for the ad8109 symbols and footprints for the ad8108 symbols and footprints for the ad8109 design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad8108 ad8109 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad8108/ad8109 rev. b | page 2 of 32 table of contents ad8108/ad8109 specifications ................................................. 3 timing characteristics (serial) .................................................. 5 timing characteristics (parallel) ............................................... 6 absolute maximum ratings ............................................................ 8 maximum power dissipation ..................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 i/o schematics ................................................................................ 17 theory of operation ...................................................................... 18 applications ................................................................................. 18 power-on reset ....................................................................... 19 gain selection ............................................................................. 19 creating larger crosspoint arrays .......................................... 20 multichannel video ................................................................... 21 crosstalk ...................................................................................... 22 pcb layout ...................................................................................... 24 evaluation board ............................................................................ 28 control the evaluation board from a pc ................................ 28 overshoot of pc printer ports data lines ............................. 28 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 9/05rev. a to rev. b updated format.................................................................. universal change to absolute maximum ratings..........................................8 changes to maximum power dissipation section........................8 change to figure 4 ............................................................................8 updated outline dimensions ........................................................30 changes to ordering guide ...........................................................30 1/02rev. 0 to rev. a universal change in nomenclature from mqfp to lqfp ............. comment added to outline dimensions ..........................27 revision 0: initial version
ad8108/ad8109 rev. b | page 3 of 32 ad8108/ad8109 specifications v s = 5 v, t a = +25c, r l = 1 k?, unless otherwise noted. table 1. parameter conditions min typ max unit reference dynamic performance ?3 db bandwidth 200 mv p-p, r l = 150 ? 240/150 325/250 mhz figure 1, figure 13 2 v p-p, r l = 150 ? 140/160 mhz figure 1, figure 13 propagation delay 2 v p-p, r l = 150 ? 5 ns slew rate 2 v step, r l = 150 ? 400/480 v/s settling time 0.1%, 2 v step, r l = 150 ? 40 ns figure 15, figure 18 gain flatness 0.05 db, 200 mv p-p, r l = 150 ? 60/50 mhz figure 1, figure 13 0.05 db, 2 v p-p, r l = 150 ? 60/50 mhz figure 1, figure 13 0.1 db, 200 mv p-p, r l = 150 ? 70/65 mhz figure 1, figure 13 0.1 db, 2 v p-p, r l = 150 ? 80/50 mhz figure 1, figure 13 noise/distortion performance differential gain error ntsc or pal, r l = 1 k? 0.01 % ntsc or pal, r l = 150 ? 0.02 % differential phase error ntsc or pal, r l = 1 k? 0.01 degrees ntsc or pal, r l = 150 ? 0.02 degrees crosstalk, all hostile f = 5 mhz 83/85 db figure 8, figure 14 f = 10 mhz 76/83 db figure 8, figure 14 off isolation, input-output f = 10 mhz, r l =150 ?, one channel 93/98 db figure 23, figure 29 input voltage noise 0.01 mhz to 50 mhz 15 nv/ hz figure 20, figure 26 dc performance gain error r l = 1 k? 0.04/0.1 0.07/0.5 % r l = 150 ? 0.15/0.25 % gain matching no load, channel-channel 0.02/1.0 % r l = 1 k?, channel-channel 0.09/1.0 % gain temperature coefficient 0.5/8 ppm/c output characteristics output impedance dc, enabled 0.2 ? figure 24, figure 30 disabled 10/0.001 m? figure 21, figure 27 output disable capacitance disabled 2 pf output leakage current disabled, ad8108 only 1/na a output voltage range no load 2.5 3 v output current 20 40 ma short-circuit current 65 ma
ad8108/ad8109 rev. b | page 4 of 32 parameter conditions min typ max unit reference input characteristics input offset voltage worst case (all configurations) 5 20 mv figure 35, figure 41 temperature coefficient 12 v/c figure 36, figure 42 input voltage range 2.5/1.25 3/1.5 v input capacitance any switch configuration 2.5 pf input resistance 1 10 m? input bias current per output selected 2 5 a switching characteristics enable on time 60 ns switching time, 2 v step 50% update to 1% settling 25 ns switching transient (glitch) measured at output 20/30 mv p-p figure 22, figure 28 power supplies supply current avcc, outputs enabled, no load 33 ma avcc, outputs disabled 10 ma avee, outputs enabled, no load 33 ma avee, outputs disabled 10 ma dvcc 10 ma supply voltage range 4.5 to 5.5 v psrr f = 100 khz 73/78 db figure 19, figure 25 f = 1 mhz 55/58 db operating temperature range temperature range operating (still air) ?40 to +85 c ja operating (still air) 48 c/w
ad8108/ad8109 r e v. b | pa ge 5 o f 3 2 timing characteristics (serial) table 2. timin g characteristics p a r a m e t e r s y m b o l m i n t y p m a x u n i t serial data setup time t 1 20 ns clk pulse wid t h t 2 100 ns serial data hold time t 3 20 ns clk pulse separ a tion, serial mo de t 4 100 ns clk to update delay t 5 0 ns update pulse width t 6 50 ns clk to data out val i d, serial mode t 7 1 8 0 n s propagation de l a y, update to switch on or off C 8 n s data load time, clk = 5 mhz, serial mode C 6.4 s clk, update rise and fall t imes C 1 0 0 n s reset time C 2 0 0 ns table 3. logic levels v ih v il v oh v ol i ih i il i oh i ol reset , ser /par clk, data i n , ce , update reset , ser /par clk, data i n , ce , update data o u t data o u t reset , ser /par clk, data i n , ce , update reset , ser /par clk, data i n , ce , update data o u t data o u t 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max ?400 a min ?400 a max 3.0 ma min load data into serial register on falling edge 1 0 1 0 data in clk 1 = latched 0 = transparent data out out7 (d3) out7 (d2) out00 (d0) transfer data from serial register to parallel latches during low level t 7 t 1 t 3 t 6 t 2 t 4 t 5 update 01068-002 f i g u re 2. ti ming d i ag r a m, s e ri al m o d e
ad8108/ad8109 r e v. b | pa ge 6 o f 3 2 timing characteristics (parall e l) table 4. timin g characteristics p a r a m e t e r s y m b o l m i n t y p m a x u n i t data setup tim e t 1 20 ns clk pulse wid t h t 2 100 ns data hold time t 3 20 ns clk pulse separ a tion t 4 100 ns clk to update delay t 5 0 ns update pulse width t 6 50 ns propagation de l a y, update to switch on or off C 8 n s clk, update rise and fall t imes C 1 0 0 n s reset time C 2 0 0 ns table 5. logic levels v ih v il v oh v ol i ih i il i oh i ol reset , ser /par clk, d0, d1, d2, d3, a0, a1, a2 ce , update reset , ser /par clk, d0, d1, d2, d3, a0, a1, a2 ce , update data o u t data o u t reset , ser /par clk, d0, d1, d2, d3, a0, a1, a2 ce , update reset ser /par clk, d0, d1, d2, d3, a0, a1, a2 ce , update data o u t data o u t 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max ?400 a min ?400 a max 3.0 ma min 1 0 1 0 d0?d3 a0?a2 clk 1 = latched update 0 = transparen t t 2 t 1 t 5 t 6 t 3 t 4 01068-003 f i g u re 3. ti ming d i ag r a m, p a r a l l e l m o de
ad8108/ad8109 r e v. b | pa ge 7 o f 3 2 table 6. o p era t ion truth ta b l e ce updat e clk data in data o u t reset ser / par operation/comment 1 x x x x x x no change in logic. 0 1 f data i data i- 3 2 1 0 the data on the serial data in line is loaded into serial register. the first bit clocked i n to the serial re gister appear s a t data out 32 clock s later. 0 1 f d0 d3, a0 a2 na in paralle l mode 1 1 the data on the parallel data lin e s, d0 to d3, are loaded into the 32-bit serial s h if t register loca tion addressed by a0 to a2. 0 0 x x x 1 x data in the 32-bit shift register t r an sfers into the parallel latches that control the switch array. latche s are transp aren t. x x x x x 0 x asynchronous operation. all outputs are disabled. remainder of logic is unchanged. d clk q s d1 q d0 3 to 8 de code r a0 a1 a2 clk ce reset d le out0 en q cl r 8 64 data in (serial) (output enable) ser/par out0 en data out parallel dat a dq clk s d1 q d0 dq clk s d1 q d0 dq clk s d1 q d0 dq clk s d1 q d0 d0 d1 d2 d3 dq clk s d1 q d0 dq clk s d1 q d0 dq clk s d1 q d0 dq clk s d1 q d0 d q clk s d1 q d0 out1 en out2 en out3 en out4 en out5 en out6 en out7 en d le out0 b2 q d le out0 b1 q d le out0 b0 q d le out1 b0 q d le out6 en q cl r d le out7 b0 q d le out7 b1 q d le out7 b2 q d le out7 en q cl r decode output enable switch matrix 01068-011 f i gure 4 . l o gic d i agr a m
ad8108/ad8109 r e v. b | pa ge 8 o f 3 2 absolute maximum ratings table 7. p a r a m e t e r r a t i n g supply voltage 12.0 v internal power dissip a tion 1 ad8108/ad810 9 80-lead plastic lqfp (st) 2.6 w input voltage v s output short-ci rcuit duration observ e pow er derating curves storage temperature range 2 ?65c to +125c 1 specif ication is f o r d e vice in f r ee air ( t a = 25 c) : 80-lead pla s tic lqf p (st): ja = 48 c/w. 2 maximum reflow t e mperatures are to jedec industry standard j-std-020. s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . maximum power dissipation the max i m u m p o w e r t h a t can b e s a fely di ssi p a t e d b y t h e ad8108/ad81 09 is limi t e d b y th e as s o c i a t e d r i s e in j u n c tio n t e m p era t ur e . th e maxim u m s a fe j u n c t i on t e m p era t ur e fo r p l a s ti c e n ca ps ula t ed d e v i c e s i s d e t e rm i n ed b y th e gla s s t r a n si ti o n t e m p era t ur e o f th e plas tic, a p p r o x ima t e l y 125c. t e m p o r a r il y exce e d i n g t h is l i m i t m a y c a us e a sh if t i n p a ramet r ic p e r f o r manc e d u e t o a chan ge i n t h e st r e s s es exer t e d on t h e di e b y t h e p a cka g e . e x ceedin g a j u nc tio n t e m p er a t u r e o f 125c f o r a n ext e n d e d p e r i o d c a n re su lt in de v i c e f a i l u r e. w h i l e t h e ad81 08/ad81 09 a r e in t e r n al l y sh o r t-cir c u i t p r ot e c t e d, t h i s m a y n o t be s u ffi c i e n t t o gua r a n t e e th a t th e m a xi m u m j u n c ti o n t e m p era t ur e (125c) is n o t exceeded u nder al l c o n d i t io ns. t o ens u re p r op er op er a t ion, i t is n e cess a r y t o ob s e r v e t h e max i m u m p o w e r d e ra t i n g cur v es s h o w n in f i gur e 5. ambient temperature ( c) 5.0 m a xim u m pow e r d i ssipa tion ( ? ) 4.0 0 ?5 0 8 0 ?40 ? 30 ?20 ? 10 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 3.0 2.0 1.0 t j = 125 c 90 01068-004 f i gure 5. m a xi m u m p o wer d i s s i pat i on v s . t e mpe r atu r e esd caution esd (electrostatic discharge) se nsit ive device . electrostatic charges as hig h as 4000 v readily accumulate on the human bod y and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharge s . ther efore, pro p er esd precautions are rec o m m ended to avoid performan c e degradation or l o ss of functiona l ity.
ad8108/ad8109 r e v. b | pa ge 9 o f 3 2 pin conf iguration and fu nction descriptions 2 agnd 3 in01 4 agnd 7 in03 6 agnd 5 in02 1 in00 8 agnd 9 in04 10 agnd 12 agnd 13 in06 14 agnd 15 in07 16 agnd 17 avee 18 avcc 19 avcc07 20 out07 11 in05 59 58 57 54 55 56 60 53 52 data out clk data in a0 ser/par update ce a1 a2 51 d0 49 d2 48 d3 47 nc 46 agnd 45 avee 44 avcc 43 avcc00 42 agnd00 41 out00 50 d1 nc = no connect 21 agnd0 7 22 a vee06/07 23 out06 24 agnd0 6 25 a v c c 05/06 26 out05 27 agnd0 6 28 a vee04/05 29 out04 30 agnd0 4 31 a v c c 03/04 32 out03 33 agnd0 3 34 a vee02/03 35 out02 36 agnd0 2 37 a v c c 01/02 38 out01 39 agnd0 1 40 a vee00/01 80 dgnd 79 dv cc 78 nc 77 nc 76 nc 75 nc 74 nc 73 nc 72 nc 71 nc 70 nc 69 nc 68 nc 67 nc 66 nc 65 nc 64 nc 63 dv cc 62 dgnd 61 r eset pin 1 ad8108/ad8109 top view (not to scale) 01068-005 f i gure 6. pin config ur ation
ad8108/ad8109 rev. b | page 10 of 32 table 8. pin function descriptions pin no. mnemonic description 1, 3, 5, 7, 9, 11, 13, 15 inxx analog inputs. xx = channels 00 through 07. 57 data in serial data input, ttl compatible. 58 clk clock, ttl compatible. falling edge triggered. 59 data out serial data output, ttl compatible. 56 update enable (transparent) low. allows serial register to connect directly to switch matrix. data latched when high. 61 reset disable outputs, active low. 60 ce chip enable, enable low. must be low to clock in and latch data. 55 ser /par selects serial data mode, low or parallel, high. must be connected. 41, 38, 35, 32, 29, 26, 23, 20 outyy anal og outputs. yy = channels 00 through 07. 2, 4, 6, 8, 10, 12, 14, 16, 46 agnd anal og ground for inputs and switch matrix. 63, 79 dvcc 5 v for digital circuitry 62, 80 dgnd ground for digital circuitry 17, 45 avee ?5 v for inp uts and switch matrix. 18, 44 avcc +5 v for in puts and switch matrix. 42, 39, 36, 33, 30, 27, 24, 21 agndxx ground for output am p. xx = output channels 00 through 07. must be connected. 43, 37, 31, 25, 19 avccxx/yy +5 v for output amplifier that is shared by channels xx and yy. must be connected. 40, 34, 28, 22 aveexx/yy ?5 v for output amplifier that is shared by channels xx and yy. must be connected. 54 a0 parallel data input, ttl compatible (output select lsb). 53 a1 parallel data input, ttl compatible (output select). 52 a2 parallel data input, ttl compatible (output select msb). 51 d0 parallel data input, ttl compatible (input select lsb). 50 d1 parallel data input, ttl compatible (input select). 49 d2 parallel data input, ttl compatible (input select msb). 48 d3 parallel data input, tt l compatible (output enable). 47, 64 to 78 nc no connect.
ad8108/ad8109 rev. b | page 11 of 32 typical perf orm ance cha r acte ristics frequency (hz) gain ( d b) 5 4 100k 1m 1g 10m 100m 3 2 ?2 1 0 ?1 ?3 0.4 0.3 0.2 0.1 ?0.3 0 ?0.1 ?0.2 ?0.4 flatness gain fla tn ess ( d b ) 2v p-p 200mv p-p r l = 150 ? 01068-012 f i g u re 7. a d 81 08 f r equenc y r e s p ons e frequency (mhz) 0.2 1 200 10 100 cros s t alk (db) ?10 ?20 ? 110 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 adjacent all hostile r l = 1k ? 01068-013 f i g u re 8. a d 81 08 c r os s t a l k v s . f r equ e nc y r l = 150 ? v out = 2v p-p frequency (hz) 100k 1m 10m 100m distortion ( d b) ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 2nd harmonic 3rd harmonic 01068-014 f i g u re 9. a d 81 08 d i s t o r t i on v s . f r eque nc y +50mv +25mv 0 ? 25mv ? 50mv 25mv/d i v 10ns/div 01068-015 f i gur e 1 0 . ad81 08 st e p re sp onse , 10 0 m v ste p +1.0v +0.5v 0 ?0.5v ?1.0v 500mv/d i v 10ns/div 01068-016 f i g u re 11. a d 8 1 0 8 step r e s p o n s e , 2 v step 2v step r l = 150 ? 01 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 10ns/div 0 0.1 0.2 ?0.1 ?0.2 0.1%/d iv 01068-017 f i gur e 1 2 . ad81 08 se ttl ing ti me
ad8108/ad8109 rev. b | page 12 of 32 frequency (hz) gain ( d b) 4 3 100k 1m 1g 10m 100m 2 1 ?3 0 ?1 ?2 0.4 0.3 0.2 ?0.2 0.1 0 ?0.1 ?0.3 flatness gain fla tn ess ( d b ) 2v p-p 200mv p-p 2v p-p 5 ?0.4 01068-018 f i gur e 1 3 . ad81 09 f r e q ue nc y re sp onse frequency (hz) 300k 1m 10m 100m cros s t alk (db) ?20 ?30 adjacent ?40 ?50 ?90 ?60 ?70 ?80 ? 100 ? 110 r l = 1k ? al l h o s t i l e 200m 01068-019 f i gur e 1 4 . ad81 09 cr o ssta l k vs . f r e q ue nc y frequency (hz) 100k 1m 10m 100m distortion ( d b) ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 2nd harmonic 3rd harmonic r l = 150 ? v out = 2v p-p 01068-020 f i gur e 1 5 . ad81 09 di st or tio n vs . f r e q ue nc y +50mv +25mv 0 ? 25mv ? 50mv 25mv/d i v 10ns/div 01068-021 f i gur e 1 6 . ad81 09 st e p re sp onse , 10 0 m v ste p +1.0v +0.5v 0 ? 0.5v ? 1.0v 0.5v/d iv 10ns/div 01068-022 f i g u re 17. a d 8 1 0 9 step r e s p o n s e , 2 v step 2v step r l = 150 ? 0 1 0 2 03 0 4 0 5 06 0 7 0 8 0 10ns/div 0 0.1 0.2 ?0.1 ?0.2 0.1%/d iv 01068-023 f i gur e 1 8 . ad81 09 se ttl ing ti me
ad8108/ad8109 rev. b | page 13 of 32 frequency (hz) 10k 100k 1m 10m ?30 ?40 ?50 ?60 ?70 ?80 ?90 p o we r s u p p l y re j e ction (db) r l = 150 ? 01068-024 f i gur e 1 9 . ad81 08 p s rr vs . f r e q ue nc y nv/ hz frequency (hz) 100k 1m 10m 10 100 56.3 31.6 17.8 10 5.63 3.16 10k 1k 100 01068-025 f i gur e 2 0 . ad81 08 v o l t a g e no i s e vs . f r e q ue nc y outp ut imp e dance ( ? ) frequency (mhz) 0.1 10 100 500 1m 100k 10k 1k 100 1 01068-026 f i gur e 2 1 . ad81 08 output im p e da nc e , di sa bl e d 5 4 3 2 1 0 10 0 ?1 0 50ns/div typical video out (rto) update input switching between two inputs 1v/d iv 10mv/d i v 01068-027 f i g u re 22. a d 8 1 0 8 switch ing t r ans i e n t (glit ch) off is olation (db) frequency (hz) 100k 10m 100m 500m 1m v in = 2v p-p r l = 150 ? ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 ? 110 ? 120 ? 130 ?4 0 ? 140 01068-028 f i gur e 2 3 . ad81 08 o ff iso l a t i o n, input - output outp ut imp e dance ( ? ) 1k 100 10 1 frequency (hz) 100k 10m 100m 500m 0.1 1m 01068-029 f i gur e 2 4 . ad81 08 output im p e da nc e , ena b le d
ad8108/ad8109 rev. b | page 14 of 32 p o we r s u p p l y re j e ction (db rti) frequency (hz) 10k 100k 1m 10m ?30 ?40 ?50 ?60 ?70 ?80 ?90 r l = 150 ? 01068-030 f i gur e 2 5 . ad81 09 p s rr vs . f r e q ue nc y nv/ hz frequency (hz) 100k 1m 10m 10 100.0 56.3 31.6 17.8 10.0 5.63 3.16 10k 1k 100 01068-031 f i gur e 2 6 . ad81 09 v o l t a g e no i s e vs . f r e q ue nc y outp ut imp e dance ( ? ) frequency (hz) 100k 10m 100m 500m 1m 100k 10k 1k 100 1 01068-032 f i gur e 2 7 . ad81 09 output im p e da nc e , di sa bl e d 5 4 3 2 1 0 10 0 ?1 0 50ns/div typical video out (rto) update input switching between two inputs 1v/div 10mv/d i v 01068-033 f i g u re 28. a d 8 1 0 9 switch ing t r ans i e n t (glit ch) ?60 ?80 ?100 ?120 ?130 ?110 ?90 ?70 ?50 off is olation (db) frequency (hz) 100k 10m 100m 500m 1m ?40 ?140 v out = 2v p-p r l = 150 ? 01068-034 f i gur e 2 9 . ad81 09 o ff iso l a t i o n, input - output outp ut imp e dance ( ? ) 1k 100 10 1 0.1 frequency (hz) 100k 10m 100m 500m 1m 01068-035 f i gur e 3 0 . ad81 09 output im p e da nc e , ena b le d
ad8108/ad8109 rev. b | page 15 of 32 inp u t imp e dance ( ? ) 1m 500m 10m 100m 100k frequency (hz) 30k 1m 100k 10k 1k 100 01068-036 f i gur e 3 1 . ad81 08 input impedan c e vs . f r equenc y gain ( d b) ?2 ?4 ?6 ?8 0 6 4 2 8 frequency (hz) 100m 1m 10m 30k 3g 1g 100k v in = 200mv r l = 150 ? c l = 18pf c l = 12pf 01068-037 f i gur e 3 2 . ad81 08 f r e q ue nc y re sp onse vs . c a pac i ti v e l o a d fla tn ess ( d b ) ?0.1 ?0.2 ?0.3 ?0.4 0 0.3 0.2 0.1 0.4 0.5 frequency (hz) 100m 1m 10m 30k 3g 1g 100k ?0.5 v in = 200mv r l = 150 ? c l = 12pf c l = 18pf 01068-038 f i g u re 33. a d 8 1 0 8 f l at nes s v s . cap a c i t i ve l oad 1 0 50ns/div 1v/div 2v/div input 0 at ? 1 v v out input 1 at +1v 5 ?1 0 update 01068-039 f i gur e 3 4 . ad81 08 s w i t c h i n g t i m e offset voltage (v) fre q ue ncy ?0.020 900 800 500 400 200 0 700 600 300 100 ? 0.010 0.000 0.010 0.020 01068-040 f i gur e 3 5 . ad81 08 o ffse t v o l t a g e di st r i butio n temperature ( c) v os (mv ) ?60 2.0 1.5 0.0 ?1.0 ?2.0 1.0 0.5 ?0.5 ?1.5 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 01068-041 f i g u re 36. a d 8 1 0 8 o f f s et v o lt ag e d r if t v s . t e mper at ur e (n or ma li z e d at 25 c )
ad8108/ad8109 rev. b | page 16 of 32 inp u t imp e dance ( ? ) 1m 500m 10m 100m 100k frequency (hz) 30k 1m 100k 10k 1k 100 01068-042 f i gur e 3 7 . ad81 09 input impedan c e vs . f r equenc y ?2 ?4 ?6 ?8 0 6 4 2 8 gain ( d b) frequency (hz) 100m 1m 10m 30k 3g 1g 100k v in = 100mv r l = 150 ? c l = 18pf c l = 12pf 01068-043 f i gur e 3 8 . ad81 09 f r e q ue nc y re sp onse vs . c a pac i ti v e l o a d gain ( d b) ?0.1 ?0.2 ?0.3 ?0.4 0 0.3 0.2 0.1 0.4 frequency (hz) 100m 1m 10m 30k 3g 1g 100k v in = 100mv r l = 150 ? c l = 18pf c l = 12pf 01068-044 f i g u re 39. a d 8 1 0 9 f l at nes s v s . cap a c i t i ve l oad 1 0 50ns/div 1v/div 2v/div input 1 at +1v 5 ?1 0 input 0 at ? 1 v v out update 01068-045 f i gur e 4 0 . ad81 09 s w i t c h i n g t i m e 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 offset voltage (v) fre q ue ncy ? 0.020 0 ?0.010 0.000 0.010 0.020 01068-046 f i gur e 4 1 . ad81 09 o ffse t v o l t a g e di st r i butio n (r ti) ?60 2.0 1.5 0.0 ?1.0 ?2.0 1.0 0.5 ?0.5 ?1.5 ? 4 0 ? 20 0 2 0 4 0 6 0 8 0 100 temperature ( c) v os (mv ) 01068-047 f i g u re 42. a d 8 1 0 9 o f f s et v o lt ag e d r if t v s . t e mper at ur e (n or ma li z e d at 25 c )
ad8108/ad8109 rev. b | page 17 of 32 i/o sche matics esd esd input v cc avee 01068-006 f i g u re 43. a n a l og i n put esd esd output v cc avee 1k ? (ad8109 only) 01068-007 f i g u re 44. a n a l og o u t p ut esd esd v cc 20k ? dgnd 01068-008 f i gure 4 5 . reset inp u t esd esd input v cc dgnd 01068-009 f i gure 4 6 . l o gi c inp u t esd esd output v cc dgnd 2k ? 01068-010 f i gure 4 7 . l o gi c o u tput
ad8108/ad8109 rev. b | page 18 of 32 theory of operation the ad8108 (g = 1) and ad8109 (g = 2) share a common core architecture consisting of an array of 64 transconductance (gm) input stages organized as eight 8:1 multiplexers with a common 8-line analog input bus. each multiplexer is basically a folded- cascode, high impedance voltage feedback amplifier with eight input stages. the input stages are npn differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, compensation and a complementary emitter follower output buffer. in the ad8108, the output of each multiplexer is fed back directly to the inverting inputs of its eight gm stages. in the ad8109, the feedback network is a voltage divider consisting of two equal resistors. this switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back terminated video load (150 ?) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02, respectively). this design also achieves high input resistance and low input capacitance without the signal degradation and power dissipation of additional input buffers. however, the small input bias current at any input will increase almost linearly with the number of outputs programmed to that input. the output disable feature of these crosspoints allows larger switch matrices to be built by simply busing together the outputs of multiple 8 8 ics. however, while the disabled output impedance of the ad8108 is very high (10 m?), that of the ad8109 is limited by the resistive feedback network (which has a nominal total resistance of 1 k?) that appears in parallel with the disabled output. if the outputs of multiple ad8109s are connected through separate back termination resistors, the loading due to these finite output impedances will lower the effective back termination impedance of the overall matrix. this problem is eliminated if the outputs of multiple ad8109s are connected directly and share a single back termination resistor for each output of the overall matrix. this configuration increases the capacitive loading of the disabled ad8109s on the output of the enabled ad8109. applications the ad8108/ad8109 have two options for changing the programming of the crosspoint matrix. in the first, a serial word of 32 bits can be provided that will update the entire matrix each time. the second option allows for changing a single outputs programming via a parallel interface. the serial option requires fewer signals, but requires more time (clock cycles) for changing the programming, while the parallel programming technique requires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming. serial programming the serial programming mode uses the device pins ce , clk, data in, update , and ser /par. the first step is to assert a low on ser /par to enable the serial programming mode. ce for the chip must be low to allow data to be clocked into the device. the ce signal can be used to address an individual device when devices are connected in parallel. the update signal should be high during the time that data is shifted into the devices serial port. although the data will still shift in when update is low, the transparent, asynchronous latches will allow the shifting data to reach the matrix. this will cause the matrix to try to update to every intermediate state as defined by the shifting data. the data at data in is clocked in at every down edge of clk. a total of 32 data bits must be shifted in to complete the programming. for each of the eight outputs, there are three bits (d0 to d2) that determine the source of its input followed by one bit (d3) that determines the enabled state of the output. if d3 is low (output disabled), the three associated bits (d0 to d2) do not matter because no input will be switched to that output. the most significant output address data is shifted in first and is followed in sequence until the least significant output address data is shifted in. at this point, update can be taken low, which will cause the programming of the device according to the data that was just shifted in. the update registers are asynchronous, and when update is low, they are transparent. if more than one ad8108/ad8109 device is to be serially programmed in a system, the data out signal from one device can be connected to the data in of the next device to form a serial chain. all of the clk, ce , update , and ser /par pins should be connected in parallel and operated as described above. the serial data is input to the data in pin of the first device of the chain, and it will ripple on through to the last. therefore, the data for the last device in the chain should come at the beginning of the programming sequence. the length of the programming sequence will be 32 times the number of devices in the chain. parallel programming while using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. in fact, parallel programming allows the modification of a single output at a time. since this takes only one clk/ update cycle, significant time savings can be realized by using parallel programming. one important consideration in using parallel programming is that the reset signal does not reset all registers in the
ad8108/ad8109 rev. b | page 19 of 32 ad8108/ad8109. when taken low, the reset signal will only set each output to the disabled state. this is helpful during power-up to ensure that two parallel outputs will not be active at the same time. after initial power-up, the internal registers in the device will generally have random data, even though the reset signal was asserted. if parallel programming is used to program one output, that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up. this will ensure that the programming matrix is always in a known state. from then on, parallel programming can be used to modify a single, or more, output at a time. in a similar fashion, if both ce and update are taken low after initial power-up, the random power-up data in the shift register will be programmed into the matrix. therefore, to prevent the crosspoint from being programmed into an unknown state, do not apply low logic levels to both ce and update after power is initially applied. programming the full shift register one time to a desired state by either serial or parallel programming after initial power-up will eliminate the possibility of programming the matrix to an unknown state. to change an outputs programming via parallel programming, ser /par and update should be taken high and ce should be taken low. the clk signal should be in the high state. the address of the output that is to be programmed should be put on a0 to a2. the first three data bits (d0 to d2) should contain the information that identifies the input that is programmed to the output that is addressed. the fourth data bit (d3) will determine the enabled state of the output. if d3 is low (output disabled), the data on d0 to d2 does not matter. after the desired address and data signals have been established, they can be latched into the shift register by a high to low transition of the clk signal. the matrix will not be programmed, however, until the update signal is taken low. thus, it is possible to latch in new data for several or all of the outputs first via successive negative transitions of clk while update is held high, and then have all the new data take effect when update goes low. this technique should be used when programming the device for the first time after power-up when using parallel programming. power-on reset when powering up the ad8108/ad8109, it is usually desirable to have the outputs come up in the disabled state. when taken low, the reset pin will cause all outputs to be in the disabled state. however, the reset signal does not reset all registers in the ad8108/ad8109. this is important when operating in the parallel programming mode. please refer to that section for information about programming internal registers after power- up. serial programming will program the entire matrix each time, so no special considerations apply. since the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. to prevent this, do not apply logic low signals to both ce and update initially after power-up. the shift register should first be loaded with the desired data, and then update can be taken low to program the device. the reset pin has a 20 k? pull-up resistor to dvdd that can be used to create a simple power-up reset circuit. a capacitor from reset to ground will hold reset low for some time while the rest of the device stabilizes. the low condition will cause all the outputs to be disabled. the capacitor will then charge through the pull-up resistor to the high state, thus allowing full programming capability of the device. gain selection the 8 8 crosspoints come in two versions, depending on the desired gain of the analog circuit paths. the ad8108 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. the ad8108 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. the ad8108 outputs have very high impedance when their outputs are disabled. the ad8109 can be used for devices that will be used to drive a terminated cable with its outputs. this device has a built-in gain of 2 that eliminates the need for a gain-of-2 buffer to drive a video line. because of the presence of the feedback network in these devices, the disabled output impedance is about 1 k?. if external amplifiers will be used to provide a g = 2, analog devices ad8079 is a fixed gain-of-2 buffer.
ad8108/ad8109 rev. b | page 20 of 32 creating l a rger crosspoint ar rays th e ad8108/a d 8109 a r e hig h den s i t y b u ildin g b l o c ks f o r c r ea ti n g cr o s sp oi n t ar r a y s of d i me nsi o ns l a rger t han 8 8. v a r i o u s fe a t ures , such as o u t p u t dis a b l e, chi p en a b le, an d gain -of-1 a nd-2 o p ti o n s, a r e useful f o r c r ea ti n g l a r g e r a rra y s . f o r v e r y la r g e a r ra y s , t h e y ca n be us e d alon g wi t h t h e ad8116, a 1 6 1 6 v i d e o c r o s s - p o i n t de vi ce. i n addi t i o n , sy s t ems t h a t r e q u ire more i n put s t h a n o u t p u t s can us e th e ad8110 and/o r t h e ad811 1, which a r e (ga i n-o f -1 and ga in-o f - 2) 16 8 cr os s p o i n t s w i t c h es. the f i rs t co n s i d era t io n in co ns t r uc t i n g a la rg er cr os s p o i n t is t o deter m i n e t h e mini m u m n u mb er o f de vice s r e q u ir e d . t h e 8 8 a r c h i t ec t u r e o f t h e ad8108/ad8109 co n t a i n s 6 4 p o in ts, whic h is a fac t o r o f 16 g r ea t e r tha n a 4 1 cr os s p o i n t . the pc bo a r d a r e a a nd p o w e r co n s um p t io n s a vi n g s a r e r e adi l y a p p a r e n t w h e n co m p a r e d t o usi n g t h es e smal ler de vices. f o r a n o n b lo ck i n g cr ossp o i n t , t h e n u m b er o f p o in ts r e q u ir e d is t h e p r o d uc t o f t h e n u m b er o f in p u ts m u l t i p lie d b y t h e n u m b er of output s . n o nbl o ck i n g re q u i r e s t h a t t h e pro g r a m m i ng of a g i ve n i n put to one or more output s d o e s not re s t r i c t t h e a v a i lab i li ty o f tha t in p u t t o b e a s o ur ce f o r a n y o t h e r o u t p u t s. s o me non b l o ck i n g c r o ssp oi n t arch ite c tures w i l l re qu ire mo re t h an t h i s mini m u m as c a l c u l a t e d ab o v e . al s o , t h ere a r e b l o c k i n g a r chi - t e ct u r e s t h a t ca n be c o n s t r u c t e d w i th f e w e r d e v i c e s th a n th i s m i nim u m. th es e s y s t em s ha v e co nn ect i vi t y a v a i la b l e o n a s t a t i s - tical basis tha t is det e r m in e d w h e n desig n in g t h e o v eral l sys t e m . the basic con c ep t in co n s tr uc tin g la rg er cr os s p o i n t a r ra ys is t o co n n ec t in p u t s in pa ralle l in a h o ri z o n t al di r e ctio n a n d t o w i r e - o r t h e o u t p u t s t o g e t h er i n t h e v e r t ical dir e c t ion. th e me a n i n g o f h o r i zon t a l and ver t ica l ca n b e st b e u n dersto o d b y lo ok in g a t a d i a g ra m. an 8 in p u t b y 1 6 o u t p u t cr os sp o i n t a r ra y can b e co n s tr uc t e d as sho w n i n f i gur e 48. this co nf ig ura t io n p a ra l l e l s tw o i n p u ts p e r ch a n nel and do e s not re q u i r e p a r a l l el i n g of an y outp ut s. i n put s a r e e a sier t o p a ral l e l t h a n o u t p u t s b e ca us e t h er e a r e lo w e r p a rasi t i cs in v o l v e d . f o r a 16 8 cr os s p o i n t , t h e ad8110 (ga i n o f 1) o r ad8111 (ga i n of 2) device can be us e d . th es e de vices a r e alread y co nf ig ured in t o a 16 8 cr oss p oin t in a s i ng l e de vic e . 8 inputs in 00?07 16 outputs out 00?15 one termination per input 8 8 8 8 8 ad8108 or ad8109 ad8108 or ad8109 01068-048 f i g u re 48. 8 16 cros s p oint a r r a y u s in g t w o a d 81 08s (u nit y g a in) or t w o a d 81 09s (g ain of 2 ) f i gur e 49 il l u s t ra t e s a 16 16 cros s p o i n t a r ra y , while a 24 24 cr os s p o i n t is il l u s t ra t e d in f i gu r e 50. the 16 16 cr os s p o i n t r e q u ir es t h a t e a ch i n p u t dr i v er dr i v e tw o in p u t s in p a ral l e l and e a ch output b e w i re - o r e d w i t h one ot he r output . t h e 2 4 2 4 c r o ssp oi n t re qu i r e s d r iv i n g t h re e i n p u t s i n p a r a l l el a n d h a v i ng t h e ou t p u t s wire-or e d in g r o u ps o f t h r e e . i t is r e q u ir e d o f t h e s y ste m pro g r a m m i ng t h a t on ly one output of a w i re d - or no d e b e ac t i ve a t a t i m e . in 00?07 00 ? 0 7 08 ? 1 5 in 08?15 out 00 ? 0 7 out 08?15 8 8 8 8 8 8 r term r term 8 8 8 8 8 8 8 8 8 8 01068-049 f i g u re 49. 1 6 1 6 cr os s p o i nt a r r a y u s ing f o u r a d 81 08s or a d 81 0 9 s in 00?07 in 08?15 in 16?23 out 16? 2 3 out 08 ? 1 5 out 00? 0 7 r term 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 r term r term 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 01068-050 f i gur e 5 0 . 24 24 cr o ssp oi nt a r r a y u s i n g nine ad8 108 s o r ad8 109 s a t s o me p o i n t, t h e n u m b er o f o u t p uts t h a t a r e wir e -o r e d b e c o me s to o g r e a t to ma i n t a i n s y ste m p e r f or manc e. th i s w i l l va r y acco r d in g to w h ich sy st e m sp e c if ic a t io n s a r e m o st im p o r t an t. f o r exa m p l e , a 64 8 cr os s p o i n t can b e cr ea t e d wi t h eig h t ad8108 /ad8109s. this desig n wil l ha v e 64 s e p a ra t e in p u ts an d ha v e t h e co r r es p o ndin g o u t p u t s o f e a ch de v i ce wir e - or e d to ge t h e r i n g r oup s of e i g h t .
ad8108/ad8109 rev. b | page 21 of 32 u s in g ad di t i o n a l cr o ssp o i n t de v i ces in t h e desig n can lo w e r t h e n u mb e r of output s t h at m u st b e w i re - o r e d to ge t h e r . f i g u re 5 1 s h o w s a b l o c k dia g ra m o f a sys t em usin g eig h t ad8108s an d tw o ad8109s to cr ea t e a n o n b l o c k ing, ga in-o f-2, 64 8 c r o ssp oin t t h a t re st r i c t s t h e wire -or ing a t t h e ou t p ut to on ly f o ur o u t p u t s. th e ra n k 1 wir e -o r e d devices ar e ad8108s, w h ich ha ve hig h er dis a b l e d ou t p u t i m p e dan c e t h a n t h e ad8109. 8 4 4 4 4 4 4 rank 2 16 8 nonblocking 16 16 blocking rank 1 (64:16) 4 4 8 8 4 4 8 8 8 8 8 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ad8109 ad8109 ad8108 ad8108 ad8108 ad8108 ad8108 ad8108 ad8108 ad8108 in 00? 0 7 out 00?07 nonblocking additional 8 outputs (subject to blocking) in 08? 1 5 in 16? 2 3 in 24? 3 1 in 32? 3 9 in 40? 4 7 in 48? 5 5 in 56? 6 3 1k ? 1k ? 1k ? 1k ? 01068-051 f i g u re 51. no nbl o c k ing 6 4 8 a r r a y w i t h g a in of 2 (6 4 16 bl ock i ng ) a d d i t i on a l ly , b y u s i n g t h e l o we r f o u r output s f r om e a ch of t h e tw o ra nk 2 ad8 109s, a b l o c k i n g 64 16 cr os s p o i n t a r ra y c a n be r e ali z e d . th er e a r e , h o we v e r , s o m e dra w b a cks to t h is t e chni q u e. the o f fs et v o l t ag es o f t h e va r i ous cas c ade d de v i ces w i l l acc u m u la te, and t h e b a ndwi d t h lim i t a t i o n s o f t h e de vi ces w i l l co m p o u nd . i n addi t i o n , t h e ext r a de vi ces wi l l con s u m e m o r e c u r r en t an d t a ke u p m o r e b o a r d sp ace. o n c e aga i n, t h e o v era l l sys t em desig n sp e c if ic a t io n s wi l l det e r m ine h o w t o mak e t h e va r i o u s trade o f f s. multichannel video the exce l l en t video s p ecif ica t ion s o f th e ad81 08/ad8109 ma k e th em id eal ca n d i d a t e s f o r cr ea tin g co m p os i t e v i d e o cr os s p o i n t swi t ch es. th e s e ca n b e made q u i t e den s e b y t aki n g ad van t a g e o f th e ad8108 /ad8109 s hig h le v e l o f in t e g r a t io n an d t h e fac t t h a t co m p osi t e vid e o r e q u ir es o n l y o n e cr os s p o i n t c h a n n e l p e r sys t em vide o cha nne l . th er e a r e, h o we v e r , o t h e r vide o fo r m a t s tha t c a n be r o u t ed wi t h t h e ad8108/ad8109 req u ir in g m o r e t h an one c r o ssp oin t chan nel p e r v i de o chan nel. s o m e sys t em s u s e twis t e d-p a ir wir i n g t o ca r r y vide o sig n als. th e s e sys t e m s u t ilize dif f er en tia l sig n als a nd can lo w e r cos t s b e c a us e t h e y us e lo w e r co st cables, co nn e c to rs, a nd ter m ina t ion m e tho d s. they als o ha v e t h e a b ili t y t o lo w e r cr os s t al k and r e je c t co m m o n -m o d e s i gn al s , wh i c h ca n be i m po r t a n t f o r eq ui p m en t t h a t o p era t es in n o isy en v i r o nmen ts o r w h er e c o mm on- m o d e v o l t a g es a r e p r es en t b e tw e e n t r a n smi t t i n g an d r e cei v in g eq ui p m en t . i n s u ch sys t em s , t h e vide o sig n als a r e dif f er en t i al; t h er e is a p o s i t i ve and ne g a t i ve ( o r i n ve r t e d ) ve rs i o n of t h e s i g n a l s . t h e s e c o m p l e me n t ar y s i g n a l s are t r ans m i tte d on to e a ch of t h e t w o w i re s of t h e t w i s te d p a i r , y i el d i ng a f i r s t - ord e r z e ro c o m m on - m o de sig n al. a t t h e r e ce i v e e n d , t h e s i g n als a r e dif f er en t i al l y r e cei v e d and con v er te d b a ck in to a sin g le- e n d e d sig n a l . w h en s w i t ching t h e s e dif f er en t i al sig n als, tw o cha nne ls a r e r e q u i r ed in t h e s w i t c h in g e l em en t t o h a n d le t h e t w o di f f e r e n ti al sig n a l s t h a t m a k e u p t h e vide o cha nnel. th us, o n e dif f er en t i a l video c h a n n e l is as sig n e d t o a p a ir o f cr os s p o i n t c h a nne ls, bo th in p u t an d o u t p u t . f o r a sin g le ad8108/ad8109, f o ur dif f er en t i a l v i de o cha nnels can b e ass i g n e d to t h e e i g h t i n p u ts a nd eig h t o u t p uts. this wi l l ef fe c t i vely fo r m a 4 4 dif f er en t i a l c r o ssp oin t s w i t c h . pr og ra mmin g s u ch a de vice wi l l r e q u ir e t h a t i n p u ts an d o u t p u t s b e p r og ra mme d in p a irs. this i n fo r m a t io n can b e de d u ce d b y in s p ec tio n o f t h e p r og ra mmin g f o r m a t o f th e ad8108/ad8109 a nd t h e r e q u ir em e n ts o f t h e syst em. ther e a r e o t h e r a n alog vi de o fo rma t s r e q u ir in g m o r e t han on e a n a l o g cir c ui t p e r vide o channel. one 2-cir c u i t fo r m a t t h a t is c o mmon ly b e ing u s e d i n s y ste m s su ch as s a tel l i t e t v , d i g i t a l ca b l e b o xes, and hig h er qua l i t y v c rs is c a l l e d s-vi de o o r y/c vid e o . t h is fo rma t ca r r ies t h e b r ig h t n e ss (l um inan ce o r y) p o r t io n o f t h e v i de o sig n a l o n on e chan n e l and t h e colo r ( c h r om i n a n c e , ch rom a , or c ) on a s e c o n d ch an n e l. since s- vi de o als o us es tw o s e p a ra t e cir c u i ts fo r o n e v i de o channel, c r e a t i ng a c r o ssp oi n t s y ste m re qu ire s ass i g n ing one video c h a n n e l to tw o cr os s p o i n t c h a n n e ls, as in th e case o f a dif f er en t i al v i de o sys t em. a s ide f r o m t h e na t u r e o f t h e vide o fo r m a t , o t h e r asp e c t s o f t h es e t w o sys t em s w i l l b e t h e s a m e . ther e a r e yet o t h e r v i de o fo r m a t s usin g t h r e e cha nne ls t o ca r r y th e v i d e o i n f o rm a t i o n. v i d e o ca m e ra s p r o d uce r g b (r ed , gr ee n , b l ue) dir e c t l y f r o m t h e ima g e s e n s o r s. r g b is als o t h e usual fo r m a t u s e d b y c o m p u t ers in ter n a l ly fo r g r a p hic s . rg b c a n b e c o n v e r te d to y , r - y , b - y for m a t , s o me t i me s c a l l e d y u v for m a t . t h e s e 3 - c i rc u i t v i d e o st a n d a rd s are re f e r r e d to a s c o m p o n e n t an a l o g v i d e o . the co m p o n en t vide o s t anda r d s r e q u ir e t h r e e c r os s p o i n t cha nnels p e r vi de o cha n n e l to ha nd le t h e s w i t chin g f u n c t i on. i n a fash io n si mi lar to t h e 2-c i r c ui t vi de o fo r m a t s, t h e in p u ts and output s are a s s i g n e d i n g r oup s of t h re e, an d t h e a ppropr i a t e log i c p r og ra mm in g is p e r f o r m e d t o r o u t e t h e vi de o sig n a l s.
ad8108/ad8109 rev. b | page 22 of 32 crosstalk m a n y sys t em s, suc h as b r o a dcast video , tha t handle n u m e r o us a n alog sig n al c h a nne ls ha ve s t r i c t r e q u ir em en ts f o r k e ep in g the v a r i ou s s i g n a l s f r om i n f l u e nc i n g an y of t h e ot he r s i n t h e s y ste m . cr os s t al k is t h e t e r m us ed t o des c r i be t h e cou p lin g o f t h e s i g n a l s of ot he r ne ar b y ch an n e l s to a g i ve n ch an n e l. w h en t h er e a r e ma n y sig n als i n p r o x imi t y in a s y s t em, as wi l l un doub t e dl y be th e cas e in a sys t em tha t us es t h e ad8108/ ad8109, t h e cros s t al k iss u es can b e q u i t e com p lex. a g o o d un d e rst a ndin g o f t h e n a t u r e o f cr o sst a l k an d s o m e def i n i t i o n o f t e r m s is r e q u ir e d t o sp e c if y a sy st em t h a t us e s o n e o r m o r e ad8108/ad81 09s. types of crossta l k cr osst a l k c a n b e p r o p a g a t e d b y m e an s o f a n y of t h r e e met h o d s . th e s e fal l in t o t h e ca teg o r i es o f e l e c t r ic f i e l d , ma g n et ic f i e l d , a nd sha r i n g o f co mm on i m p e dan c es. this s e c t i o n w i l l ex pla i n t h es e ef fe c t s. e v er y co n d uc tor ca n b e b o t h a r a di a t o r o f ele c t r ic f i elds a nd a re c e ive r of el e c t r i c f i el ds . t h e el e c t r i c f i el d c r o sst a l k me chani s m o c c u rs w h en t h e e l e c t r ic f i e l d c r e a t e d b y t h e t r a n smi t t e r p r op ag a t e s ac ro ss a st r a y c a p a c i t a nc e ( e . g . , f r e e sp ac e ) and c o upl e s w i t h t h e re c e ive r and i n d u c e s a vol t ag e. thi s vol t age i s an u n w a n t e d c r o sst a l k s i g n a l i n an y ch an n e l t h a t re c e ive s i t . c u r r en ts f l o w ing in cond uc t o rs cr ea t e ma g n etic f i e l ds tha t cir c u l a t e a r o u nd t h e c u r r en t s . th e s e ma g n et ic f i e l ds w i l l t h en g e n e ra t e v o l t a g es in an y o t h e r co n d uct o r s w h os e p a th s t h ey lin k . t h e u ndesir e d i n d u ce d vol t a g es i n t h es e ot h e r cha n nels a r e c r o sst a l k s i g n a l s . the chan nel s t h a t c r o sst a l k c a n b e s a i d to ha v e a m u t u al ind u c t a n ce tha t co u p les sig n als f r o m o n e c h a n ne l t o anot he r . the p o wer s u p p lies, g r o u n d s, and o t h e r sig n al r e t u r n p a t h s o f a m u l t icha nne l sy s t em a r e g e n e ra l l y s h a r e d b y t h e va r i o u s ch an n e l s . whe n a c u r r e n t f r om one ch an n e l f l ow s i n o n e of t h es e p a t h s, a vol t a g e t h a t is de v e l o p e d acr o s s t h e im p e dan c e b e c o me s an i n pu t c r o sst a l k s i g n a l for ot he r channel s t h a t share th e co mm o n i m pe d a n c e . al l t h es e s o ur ce s o f cr os s t al k a r e v e c t o r q u an t i t i es, s o t h e ma g n i t u d es ca nn o t sim p l y b e adde d t o g e t h er to ob ta in t h e t o t a l cr os s t al k. i n fac t , t h er e a r e condi t i on s w h er e dr i v i n g addi t i o n a l cir c ui ts in p a r a l l el i n a g i ve n conf igur a t io n ca n ac tua l ly r e d u ce t h e c r o sst a l k. area s of crossta l k f o r a p r ac tical ad8108/ad81 09 cir c ui t, i t is req u ir ed t h a t i t b e mou n te d to s o me s o r t of c i rc u i t b o ard to c o n n e c t i t to p o we r s u p p l i e s a n d m e a s ur e m en t e q ui p m en t . g r e a t ca r e h a s been t a k e n t o cr e a t e a cha r ac t e r i za t i o n b o a r d (a ls o a v a i lab l e as an e v a l ua t i o n b o a r d) t h a t adds m i nim u m cr o sst a l k to t h e i n t r in si c de vic e . this, ho w e v e r , ra is es t h e is s u e t h a t a sy s t em s cr os s t al k is a co m b in a t i o n o f th e in trin si c cr os s t al k o f t h e de vices in a d d i t i on to t h e c i rc u i t b o ard to w h i c h t h e y are mou n te d. i t i s i m p o r t a n t to t r y to s e p a r a te t h e s e t w o are a s of c r o sst a l k w h e n a tte m p t i ng to m i ni m i z e it s e f fe c t . i n ad di ti o n , cr os s t al k ca n occur a m o n g th e in p u t s t o a c r o ssp oi n t a n d among t h e output s . i t c a n a l s o o c c u r f r om i n put t o o u t p u t . t e c h n i q u e s w i ll be di scu s sed f o r di a g n o s i n g wh i c h p a r t o f a sys t em is co n t r i b u tin g t o cr os s t al k. meas uring c r os s t alk cr osst a l k is m e asur e d b y a p ply i n g a sig n a l t o on e o r m o r e c h a nne ls an d meas ur in g t h e r e l a ti v e str e n g th o f tha t sig n al o n a desir e d s e le c t e d cha nnel. t h e me asur emen t is u s ua l l y ex p r ess e d as db do w n f r o m t h e ma g n i t u d e o f t h e t e s t sig n al . th e cr os s t al k is exp r es s e d b y : () () ( ) s atest s asel xt 10 log 20 = w h er e s = j is t h e l a place t r a n s f o r m va r i a b le , as e l ( s ) is t h e a m pli t ude o f t h e cr os s t al k- i n d u ce d sig n al in t h e s e le c t e d cha nnel, and at e s t ( s ) is t h e a m pli t u d e o f t h e t e s t sig n al . i t can b e s e e n t h a t c r o sst a l k i s a f u nc t i o n of f r e q u e nc y , b u t no t a f u nc t i o n of t h e m a g n itu d e of t h e te st s i g n a l ( t o f i r s t ord e r ) . i n a d d i t i on , t h e cr osst a l k sig n a l w i l l ha ve a phas e r e la t i ve t o t h e t e st sig n a l ass o c i a t e d w i t h i t . a netw o r k a n alyzer is m o st co mm onl y us ed to m e as ur e c r o sst a l k o v e r a f r e q u e nc y r a nge of in te re st . i t c a n p r o v ide b o t h ma g n i t u d e and phas e info r m a t i o n a b ou t t h e cros s t al k sig n al . a s a cr os sp o i n t sys t em o r de vi c e g r o w s la rg er , t h e n u m b er o f t h e o r e t i ca l cr o s st a l k com b in a t i o n s a nd p e r m u t a t io n s ca n b e com e ext r e m e l y la rg e . f o r exa m ple , i n t h e cas e o f t h e 8 8 ma tr ix o f the ad8108/ad8109, w e can exa m ine the n u m b er o f c r o sst a l k te r m s t h a t c a n b e c o ns i d e r e d for a s i ng l e ch an nel, s a y in00 in p u t. in0 0 is p r og ra mm ed t o co nn ec t t o o n e o f t h e ad8108/ad81 09 o u t p u t s w h ere the m e as ur emen t can be made . w e can f i rs t m e as ur e t h e cr os s t al k t e r m s as s o c i a t e d w i t h dr ivi n g a te st s i g n a l i n to e a ch of t h e ot h e r s e ve n i n put s one a t a t i me. w e can t h e n m e as ur e t h e cr os s t al k t e r m s as s o c i a t e d w i t h dr i v in g a p a r a l l el test sig n a l i n to a l l s e ve n o t h e r in p u ts t a k e n t w o at a t i m e i n a l l p o s s i b l e c o m b i n at i o n s , a n d t h e n t h r e e at a t i m e , e t c., un t i l t h er e is o n l y one wa y t o dr i v e a t e s t sig n al in t o all sev e n o t h e r in p u t s . e a ch o f t h e s e c a s e s is leg i t i ma t e ly dif f er en t f r o m t h e ot hers a nd mig h t y i eld a u n iq ue v a l u e d e p e nding o n t h e res o l u t i o n o f t h e m e as ur e m en t sys t em, b u t i t is ha r d l y p r ac t i cal t o m e as ur e al l th e s e t e rm s a n d th en t o s p eci f y th em . i n ad di ti o n , th i s d e scri be s t h e c r o sst a l k m a t r ix for j u st one in pu t chan nel. a s i mi l a r cr os s t al k ma tr ix ca n be p r o p os e d f o r ev er y o t h e r in p u t. i n add i t i on, if t h e p o ssi b le com b i n a t io n s and p e r m u t a t io n s fo r co nn e c t i n g in pu ts t o t h e o t h e r (n o t us e d fo r me as ur emen t) o u t p uts a r e t a k e n i n t o co n s idera t io n, t h e n u m b e r s ra t h er
ad8108/ad8109 rev. b | page 23 of 32 qu i c k l y g r o w to a s t r onom i c a l pr op or t i ons . i f a l a r g e r c r o ssp oi n t a r ra y o f m u l t i p le ad8108/ad8 109s is co n s tr uc t e d , t h e n u m b ers g r o w l a rge r st i l l. effect of i m p e da nc es on c r o s s t alk the i n p u t si de c r o sst a l k can b e i n f l uen c e d b y t h e o u t p ut im p e dan c e o f t h e s o ur ces t h a t dr i v e t h e in pu ts . the lo w e r t h e im p e dan c e o f t h e dr i v e s o ur c e , t h e lo w e r t h e ma g n i t u d e o f t h e c r o sst a l k. t h e d o minan t c r o sst a l k me c h anis m on t h e i n p u t s i de i s c a p a c i t i ve c o upl i ng . t h e h i g h i m p e d a nc e i n put s d o not h a v e sig n if ican t c u r r en t f l o w t o cr e a te ma g n et ica l ly i n d u ce d cr osst a l k. h o w e ver , sig n if ican t c u r r en t can f l o w t h r o ug h t h e in p u t t e r m ina t io n r e sis t o r s a n d th e lo o p s t h a t dr i v e them. th us , t h e pc b o a r d o n t h e i n p u t side ca n con t r i b u te to ma g n et i c a l ly co u p led cr os s t al k. o b v i ou sly , s o me sub s e t of a l l t h e s e c a s e s m u st b e s e l e c t e d to b e us e d as a gui d e fo r a p r ac t i ca l m e a s ur e o f cr osst a l k. o n e c o mmon me t h o d is to me asu r e a l l ho st i l e c r o sst a l k. thi s te r m m e an s t h a t t h e cr osst a l k t o t h e s e le c t e d cha n nel is m e a s ur e d w h i l e a l l ot her sy stem cha n nels a r e dr i v en in p a r a l l el. i n gener a l, t h is w i l l y i e l d t h e w o rst cr osst a l k n u m b er , b u t t h is is n o t a l w a y s t h e cas e d u e t o t h e v e c t o r na t u r e o f t h e cr os s t al k sig n al . oth e r use f ul cr os s t alk m e as ur em en t s a r e t h ose cr ea t e d b y o n e n e a r est neig h b or o r b y t h e tw o n e a r est neig h b ors o n ei t h er side. th e s e cr os s t al k m e as ur e m en ts wi l l g e n e ral l y b e hig h er t h an th ose o f m o r e di s t a n t c h a n n e ls, so th ey ca n se r v e a s a w o r s t- ca s e m e as ur e f o r a n y o t h e r 1-c h ann e l o r 2-c h a n n e l cr os s t alk me a s u r e m e n t s . f r o m a cir c u i t st a n d p oin t , t h e i n p u t cr osst a l k m e chanism lo oks lik e a c a p a ci t o r co u p lin g t o a r e sis t i v e lo ad . f o r lo w f r e q uen c ies, t h e ma g n i t ude o f t h e cr os s t al k wi l l b e g i v e n b y ( ) [ ] s m c s r xt = 10 log 20 inp u t and o u t p ut c r os s t alk w h er e r s is the s o ur ce r e sis t a n c e , c m is t h e m u t u a l c a p a ci t a n c e b e tw e e n t h e t e st sig n a l cir c ui t and t h e s e le c t e d cir c ui t, and s is t h e l a place t r ansfo r m va r i a b le . the f l exi b le p r og ra mmin g ca p a b i li ty o f t h e ad8108/ad8109 ca n be us e d t o dia g n o s e w h et h e r cr os s t al k is o c c u r r i n g m o r e on t h e in p u t si de or t h e o u t p ut side . s o m e exa m pl es a r e i l l u s t ra t i ve . a g i v e n in p u t cha nne l (in03 in t h e middle fo r t h is exa m ple) ca n be p r og ra mm e d t o dr i v e o u t03. th e in p u t t o in03 is j u s t t e r m ina t e d t o g r o u n d ( v ia 50 ? o r 75 ?) a n d no sig n al is ap p l i e d . f r o m th e eq ua t i o n , i t ca n be obse r v ed th a t th i s cr os s t alk m e chanism has a hig h -p ass n a t u r e ; i t can b e m i nimi ze d b y re d u c i ng t h e c o upl i ng c a p a c i t a nc e of t h e i n put c i rc u i t s a n d lo w e r i n g t h e o u t p u t im p e dan c e o f t h e dr i v ers. i f t h e in pu t is dr i v en f r o m a 7 5 ? t e r m ina t e d ca b l e , t h e i n p u t cr os s t al k can b e r e d u ce d b y b u f f er in g t h is sig n a l wi t h a lo w o u t p u t im p e dan c e bu f f e r . a l l th e o t h e r i n p u t s a r e d r i v e n i n pa r a ll e l w i th th e s a m e t e s t sig n a l (p rac t ica l ly t h is is p r o v id e d b y a dist r i b u t i o n a m pl if ier), wi t h a l l ot her o u t p uts excep t ou t03 dis a b l e d . since g r o u nde d in03 is p r og ra mm e d t o dr i v e o u t03, t h er e sh o u ld be n o sig n al p r es en t. an y sig n al tha t is p r es en t can be a t tr i b u t ed t o t h e o t h e r s e v e n h o s t ile in p u t sig n als be c a us e n o o t h e r o u t p u t s a r e dr i v e n . (t h e y a r e all d i s a b l ed . ) t h us, thi s m e th od m e asur e s th e all- h o s t ile in p u t con t r i b u tion t o cr os s t al k in t o i n 0 3 . of co urs e , t h e m e t h o d ca n b e us e d fo r o t h e r i n p u t chan n e ls and com b ina t ions o f h o s t ile in p u t s . on t h e o u t p ut side, t h e cr o sst a l k can b e r e d u ce d b y dr i v in g a lig h t e r lo ad . al t h o u g h t h e ad8 108/ad8109 is s p ecif ie d wi t h exce l l en t dif f er en t i al ga i n an d phas e w h e n dr iv i n g a s t anda r d 150 ? video lo ad , t h e cr os s t al k wil l be hig h er t h a n t h e minim u m ob t a i n a b le d u e t o t h e hig h o u t p u t c u r r en ts. th es e c u r r en ts w i l l i n d u ce cr osst a l k v i a t h e m u t u a l ind u c t an ce o f t h e o u t p u t p i n s and bon d wir e s o f t h e ad8108/ad8109. f r om a c i rc u i t s t an d p o i n t , t h i s output c r o sst a l k me ch a n i s m lo oks li k e a t r ansfo r m e r , wi t h a m u t u a l i n d u c t an ce b e tw e e n t h e windin g s, tha t dr i v es a lo ad r e sis t o r . f o r lo w f r eq uen c ies, t h e ma g n i t u d e o f t h e cr os s t al k is g i ven b y f o r o u t p u t cr os s t alk m e as ur em en t , a si n g le in p u t c h a n n e l i s dr i v en (i n00, fo r ex a m ple) a nd a l l o u t p uts o t h e r t h a n a g i ve n o u t p u t (in 03 in th e m i ddl e ) a r e p r ogra m m ed t o co n n ect t o in00. o u t03 is p r og ra mm ed to co nn ec t t o in07 (fa r a w a y f r o m in00), whic h is t e r m ina t e d t o g r o u nd . th us o u t03 s h o u l d n o t ha v e a sig n al p r es e n t sin c e i t is li s t enin g t o a q u ie t in p u t. an y sig n al meas ur ed a t t h e o u t03 ca n be a t tr ib u t e d t o t h e ou t p u t cr os st al k o f t h e o t h e r s e v e n h o s t i l e ou t p uts. a g a i n, t h is met h o d can b e m o dif i e d to m e a s ur e o t h e r cha nnels an d o t h e r cr ossp o i n t ma t r ix com b in a t io n s . ( ) l r s mxy xt = 10 log 20 w h er e mxy is t h e m u t u al ind u c t a n ce o f o u t p u t x t o o u t p u t y , a nd r l is t h e lo ad r e sist an ce o n t h e me asur e d ou t p ut. t h is cr osst a l k m e chanism can b e m i nimi ze d b y k e e p in g t h e m u t u a l ind u c t an c e lo w a nd i n cr e a sing r l . th e m u t u al i n d u cta n ce c a n b e k e p t lo w b y i n cr e a sing t h e sp acin g o f t h e cond uc to rs an d mini mi zi n g t h ei r p a ra l l el len g t h .
ad8108/ad8109 rev. b | page 24 of 32 pcb layout e x t r em e ca r e m u s t b e exer cis e d t o mini mi ze addi t i o n al cr os s t al k g e n e ra t e d b y t h e sys t e m cir c ui t bo a r d(s). th e a r e a s t h a t m u st b e ca ref u l l y det a i l e d ar e g r o u n d in g , shie l d ing, sig n a l rou t ing , and sup p ly b y p a ss ing . the p a c k a g in g o f th e ad8108/ad8109 is desig n e d t o he l p k e ep t h e cr osst a l k t o a mi ni m u m. e a ch i n p u t is s e p a ra t e d f r o m e a ch ot he r i n put b y a n an a l o g g r ou n d pi n . a l l of t h e s e a g n d s sh o u l d b e d i r e c t ly co nn e c te d to t h e g r o u nd plane o f t h e c i r c ui t b o a r d . t h e s e g r o u nd p i ns p r o v i d e sh iel d i n g, lo w im p e dan c e r e t u r n p a t h s, and ph ysic al s e p a r a t i o n fo r t h e i n pu ts. al l o f t h es e he l p t o r e d u ce c r os s t al k. e a ch output i s s e p a r a te d f r om it s t w o ne i g hb or i n g output s b y a n a n alog g r o u n d p i n in addi tion t o a n a n alog s u p p l y p i n o f o n e p o la r i ty o r th e oth e r . e a ch o f t h es e a n alog s u p p l y p i n s p r o v ides p o w e r t o t h e o u t p u t s t a g es o f o n l y t h e tw o n e a r es t o u t p u t s. t h e s e s u pp l y pi ns an d an a l o g g r ou nd s prov i d e s h i e l d i n g , ph y s ica l s e p a ra t i o n , an d a lo w i m p e dan c e su p p ly fo r t h e output s . in d i v i du a l b y p a ss i n g of e a ch of t h e s e s u pply pi ns w i t h a 0.01 f c h i p ca p a ci t o r dir e c t l y t o th e g r o u nd p l a n e minimizes hig h f r e q u e nc y ou t p ut c r o sst a l k v i a t h e me chan is m of shar ing co mm on im p e da n c es. e a c h o u t p u t als o has a n o n -chi p co m p en s a tion ca p a ci t o r t h at i s i n d i v i du a l ly t i e d to t h e n e ar b y an a l o g g r ou n d pi ns a g nd00 th r o ug h a g nd0 7 . thi s t e c h niq u e r e d u ce s c r os s t al k b y p r e v e n t i n g t h e c u r r en ts t h a t f l o w in t h es e p a t h s f r o m s h a r in g a co mm on i m p e da n c e on t h e ic a nd i n t h e p a cka g e p i n s . th e s e a g nd xx sig n al s s h o u l d al l be dir e c t l y co nn e c t e d t o t h e g r o u n d pl ane. the i n p u t and ou t p ut sig n a l s wi l l ha ve m i ni m u m cr o sst a l k if t h e y a r e lo ca t e d b e tw e e n g r o u nd plan es o n l a yers a b o v e and b e lo w , an d s e p a r a te d b y g r o u nd in b e tw e e n . v i a s sh o u l d b e lo ca t e d as clos e t o t h e ic as p o ssi b l e t o c a r r y t h e in pu ts and o u t p uts t o t h e i n n e r la yer . th e o n l y place t h e i n p u t and o u t p ut sig n als s u r f ace is a t t h e in p u t t e r m ina t ion r e sis t o r s a n d t h e o u t p u t s e r i es bac k -t er mina tio n r e sis t o r s. th e s e sig n als sh o u ld als o be s e p a ra t e d , t o t h e ext e n t p o s s i b le, as s o on as t h ey em erge fr o m t h e i c p a c k a g e . o p t i m i ze d fo r v i de o a p pli c a t io ns, a l l sig n a l i n p u ts a nd o u t p u t s a r e t e r m ina t e d wi t h 75 ? r e sis t o r s. s t r i plin e t e chniq u es a r e us e d t o achie v e a charac t e r i st ic i m p e dan c e o f 75 ? o n t h e sig n a l in p u t an d o u t p u t lin e s. f i gur e 5 2 s h o w s a cr os s s e c t io n o f on e of t h e i n put or output t r a c k s a l ong w i t h t h e ar r a nge m e n t of t h e p c b l a y e r s . i t s h ou l d b e no te d t h a t u n u s e d re g i ons of t h e f o u r l a y e rs are f i l l e d up w i t h g r ou nd pl ane s . a s a re s u lt , t h e i n put a nd o u t p u t trac es, in addi tion to ha vin g con t r o l l ed im p e dan c es , a r e w e ll s h i e ld e d . w = 0.008" (0.2mm) a = 0.008" (0.2mm) b = 0.024" (0.6mm) h = 0.011325" (0.288mm) t = 0.00135" (0.0343mm) top layer signal layer power layer bottom layer 01068- 058 f i g u re 52. cros s s e c t ion of input and o u t p ut t r aces the b o a r d has 16 bn c typ e co nn e c t o rs: e i g h t i n p u ts an d e i g h t o u t p uts. th e conn e c t o rs a r e a r ra n g e d in tw o cr es cen t s a r o u nd th e de vice . a s c a n b e s een f r o m f i gur e 53, this r e s u l t s in al l e i gh t in p u t s i gnal tra c e s a n d all e i gh t s i gn al o u t p u t tra c e s h a vi n g t h e s a me l e ng t h . this is u s e f u l i n te st s su ch as a l l - ho st i l e cr os s t al k w h er e t h e phas e r e la t i o n s h i p and dela y b e tw e e n sig n als n e e d s t o be main ta in e d f r o m in p u t t o o u t p u t . the t h r e e p o w e r s u p p l y p i n s a v c c , d v c c , and a v ee sh o u l d be co nn ec t e d t o g o o d q u ali t y , lo w n o is e , 5 v su p p lies. w h er e t h e s a me 5 v p o we r suppl i e s are u s e d for an a l o g and d i g i t a l, sep a ra t e ca b l es s h o u ld be r u n f o r th e p o w e r s u p p l y t o th e e v a l u a t i on b o ard s an a l o g a n d d i g i t a l p o we r supply pi ns . a s a g e n e ral r u le , eac h p o w e r su p p l y p i n (o r gr o u p o f ad j a cen t p o w e r s u p p l y p i n s ) sh o u ld be lo cal l y de co u p le d wi th a 0.01 f ca p a ci t o r . i f t h er e is a s p ace co ns tra i n t , i t is m o r e im p o r t a n t t o d e c o up l e an a l o g p o we r s u pp l y pi ns b e f o re d i g i t a l p o we r s u pp l y p i n s . a 0.1 f c a p a ci t o r , lo c a t e d r e as o n a b l y c l os e t o t h e p i n s , ca n be us e d t o deco u p le a n u m b er o f p o w e r s u p p l y p i n s . f i nal l y a 10 f ca p a c i t o r s h o u ld be us e d t o deco u p le p o w e r s u p p lies as th ey co m e o n t o th e boa r d .
ad8108/ad8109 rev. b | page 25 of 32 01068-053 f i g u re 53. co mpon ent sid e s ilk s c r e e n 01068-054 f i gur e 5 4 . boar d lay o ut ( c om p o ne nt si de )
ad8108/ad8109 rev. b | page 26 of 32 01068-055 f i g u re 55. bo a r d la yout ( s ig n a l l a yer) 01068-056 f i gur e 5 6 . boar d lay o ut (p o w e r p l ane )
ad8108/ad8109 rev. b | page 27 of 32 01068-057 f i gure 57. boar d lay o ut (bottom lay e r)
ad8108/ad8109 rev. b | page 28 of 32 evaluation board a 4-l a yer eval ua tio n bo a r d f o r th e ad8108/ad8109 is a v a i la b l e. the e x ac t s a me b o a r d and ex t e r n al com p one n ts a r e u s e d fo r e a ch de vic e . th e o n ly dif f er en ce is t h e de vic e i t s e lf, w h ich o f fers a s e l e c t i o n of a g a i n of u n it y or g a i n of 2 t h rou g h t h e a n a l o g cha nnels. t h is b o a r d has b e en ca r e f u l l y la id o u t a nd teste d to d e m o n s t r a t e t h e s p eci f ie d h i g h s p e e d p e rf o r ma n c e o f t h e de vice . f i g u r e 60 s h o w s th e sc h e m a ti c o f th e ev al ua ti o n b o a r d . f i g u r e 53 sho w s t h e com p o n e n t side s i l k -s cr e e n . the l a yo u t s o f t h e bo a r d s f o ur la yers a r e g i v e n in f i gur e 5 4 , f i gur e 55, f i g u r e 56, a nd f i gur e 57. t h e e v a l u a t i on b o ard p a ck age i n clu d e s t h e fol l o w i n g : ? f u ll y po p u la t e d bo a r d w i t h bn c- typ e co nn ecto r s . ? w i ndo ws ? - b a s e d s o f t w a re f o r c o n t ro l l i n g t h e b o ard f r om a pc v i a t h e p r in ter p o r t . ? c u sto m cab l e to co nn e c t e v a l u a t io n b o a r d to p c . ? disk con t a i ning g e r b er f i les o f b o a r d l a yo u t . contr o l the evalua tion boar d from a pc the e v a l ua t i on b o a r d i n cl u d es w i ndo ws -b as e d co n t r o l s o f t wa re a n d a cus t o m ca b l e th a t co nn ects th e boa r d s d i g i tal in t e rfa c e t o th e p r i n t e r po r t o f th e pc. th e w i rin g o f th i s ca b l e i s sh o w n in f i gur e 58. th e s o f t wa r e r e q u ir es w i ndo ws 3.1 o r la t e r t o o p era t e. t o in st al l t h e s o f t wa r e , in s e r t t h e disk l a b e le d di s k 1 o f 2 in to t h e p c and r u n t h e f i le ca l l e d s e t u p . e x e. a d d i t i o n a l in st a l la t i o n in st r u c t io n s wi l l b e g i v e n o n -s cr e e n . b e fo r e b e g i nn in g i n st a l la t i on, i t is i m p o r t a n t t o t e r m in a t e an y o t h e r w i ndo ws a p plic a t io n s t h a t a r e r u nning. clk data in reset update ce dgnd molex 0.100" center crimp terminal housing 1 6 d-sub 25 pin (male) 14 1 25 13 evaluation board pc 2 3 4 5 6 25 3 1 4 5 2 6 signal data in ce reset update clk dgnd molex terminal housing d-sub-25 01068-059 f i g u re 58. ev aluat i on b o a r d- pc co nn ec t i o n cab l e w h en yo u l a u n ch t h e cr os s p o i n t co n t r o l s o f t w a r e , yo u wi l l b e a s ke d to s e l e c t t h e pr i n te r p o r t . m o st mo de r n p c s h a ve on ly o n e p r in t e r p o r t , us ual l y cal l ed lpt1. h o w e v e r , s o m e la p t o p co m p u t ers us e t h e prn p o r t . f i g u re 5 9 s h o w s t h e m a i n s c re e n of t h e c o n t ro l s o f t w a re i n it s ini t ial r e s e t sta t e (al l o u t p u t s o f f ) . u s in g t h e mo us e , a n y in p u t ca n be co nn e c t e d wi t h on e o r mo r e o u t p u t s b y s i m p l y c l ic kin g o n t h e a p p r o p r i a t e radio b u t t ons in t h e 8 8 o n -s cr e e n a r ra y . e a ch t i me a b u tton i s cl i c ke d on, t h e s o f t w a re a u tom a t i c a l l y s e nds an d la tches t h e r e quir e d 32-b i t da t a st r e am to t h e e v a l u a t i on b o ard. a n output c a n b e tu r n e d of f b y cl i c k i ng t h e a ppropr i a t e butt on i n t h e of f c o lu m n . t o tu r n of f a l l output s , cl ick on res e t . the s o f t wa r e o f fers v o la t i le an d n o n v ola t i l e s t o r a g e o f co nf igura t io n s . f o r v o la t i le st o r a g e , u p t o tw o c o nf igura t io n s ca n b e sto r e d and r e ca l l e d usi n g t h e m e m o r y 1 a nd m e m o r y 2 b u f f ers. th es e f u n c t i on i n an iden t i cal fashio n to t h e m e m o r y on a p o c k e t c a l c u l a t or . f o r no n v o l a t i l e s t or age o f a co nf igur a t io n, t h e s a ve s e tu p and lo ad s e t u p f u nc t i o n s can b e us e d . thi s sto r e s t h e co nf igur a t io n as a d a t a f i le o n disk. o v ershoot of p c p r in t e r po rt s d a t a lin e s the da t a li n e s on s o m e p r i n t e r p o r t s ha v e exce s s i v e o v ersh o o t. o v ers h o o t o n t h e pin t h a t is us e d as t h e s e r i a l clo c k (p in 6 o n th e d-s u b-25 c o nn ec t o r) ca n c a us e co mm unic a t io n p r ob lem s . this o v ersh o o t ca n b e eli m in a t e d b y co nn e c t i ng a ca p a c i to r f r om t h e c l k l i ne o n t h e e v a l u a t i on b o ard to g r ou nd. a p a d has b e e n p r o v ide d o n t h e s o lder side o f t h e e v al ua t i on b o a r d t o a l l o w t h i s c a p a c i tor to b e s o l d e r e d i n to pl a c e. d e p e nd i n g on t h e o v ersh o o t f r o m t h e p r in ter p o r t , t h is ca p a c i t o r ma y ne e d t o b e as la rg e as 0.01f 01068- 060 f i g u re 59. ev aluat i on b o a r d cont ro l p a ne l
ad8108/ad8109 rev. b | page 29 of 32 75 ? avee 41 40 39 2 1 input 00 input 00 agnd 4 3 input 01 input 01 agnd 6 5 input 02 input 02 agnd 8 7 input 03 input 03 agnd 10 9 input 04 input 04 agnd 12 11 input 05 input 05 agnd 14 13 input 06 input 06 agnd 16 15 input 07 input 07 agnd 59 data out 57 data in p2-5 p2-4 p2-2 p2-3 p2-1 p2-6 dgnd r eset ce ser /pa r up date clk a0 a1 a2 d0 d1 d2 d3 62 61 60 58 56 55 54 53 52 51 50 49 48 serial mode jump r25 20k ? dvcc 42 avcc 38 37 36 avee 35 34 33 avcc 32 31 30 avee 29 28 27 avcc 26 25 24 avee 23 22 21 20 agnd output 00 avee agnd output 01 avcc agnd output 02 avee agnd output 03 avcc agnd output 04 avee agnd output 05 avcc agnd output 06 avee agnd output 07 avcc 19 avcc avcc 18 avcc avee 17 avee 45 avee avee 44 avcc avcc 43 avcc avcc ad8108/ad8109 dvcc dgnd nc avee agnd avcc nc p1-1 cr1 cr2 + + + p1-2 p1-3 p1-4 p1-5 p1-6 p1-7 0 .1 f1 0 f 0.1 f1 0 f 0.1 f1 0 f 1n4148 nc = no connect nc p3- 1 p3- 2 p3- 3 p3- 4 p3- 5 p3- 6 p3- 7 p3- 8 p3- 9 p3- 1 0 p3- 1 1 p3- 1 2 p3- 1 3 p3- 1 4 63 0.01 f 79 dvcc dvcc 80 46 dvcc dvcc dgnd agnd 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 01068-052 f i g u re 60. ev aluat i on b o a r d s c h e m a t i c
ad8108/ad8109 rev. b | page 30 of 32 outline dimensions compliant to jedec standards ms-026-bdd 0.15 0.05 1.45 1.40 1.35 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 top view (pins down) 1 21 41 40 60 61 80 20 12.00 bsc sq 0.50 bsc lead pitch 0.27 0.22 0.17 14.00 bsc sq 1.60 max 0.75 0.60 0.45 view a pin 1 f i g u re 61. 8 0 -l ead l o w p r of i l e q u ad f l at p a ckag e [l qf p ] (st - 80-1) di me nsio ns sho w n i n mi ll im e t e r s ordering guide 1 model temperature r a nge package descri ption package option ad8108ast ?40c to +85c 80-lead low prof ile quad flat package [lqfp] st-80-1 ad8108astz 2 ?40c to +85c 80-lead low profile quad flat package [lqfp] st-80-1 ad8109ast ?40c to +85c 80-lead low prof ile quad flat package [lqfp] st-80-1 ad8109astz 2 ?40c to +85c 80-lead low profile quad fl at package [lqfp] st-80-1 ad8108-eb evaluation bo ar d ad8109-eb evaluation bo ar d 1 d e t a i ls of t h e l e a d fi n i sh com p osi t i o n ca n be f o un d on t h e ad i web s i t e a t www.analog.com by reviewing the m a terial des c ri ptio n of each r e levant package. 2 z = pb-free part.
ad8108/ad8109 rev. b | page 31 of 32 notes
ad8108/ad8109 rev. b | page 32 of 32 notes ? 2005 an alog dev i ces, inc. all rights reserve d . t r ad emar ks an d registered tra d emar ks are the prop erty of their respective owners . c01068C0 C 9/05(b)

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